module project3_multiplier (iClk, iReset, iReady, oDone, iMultiplier, iMultiplicand, oProduct, multiplicand,product,stateregister,shiftregister13,shiftregister7);

input iClk, iReset, iReady;
input [7:0] iMultiplier, iMultiplicand;

output oDone;
output [15:0] oProduct;
output reg [6:0] multiplicand;
output reg [13:0] product;
output reg [7:0] stateregister;
output reg [12:0] shiftregister13;
output reg [6:0] shiftregister7;

wire [6:0] wmultiplicand;
wire [6:0] w1product,w2product;
wire [12:0] frontproduct,backproduct;
wire [6:0] frontstateregister,backstateregister;
wire [7:0] wstateregister; 
wire [6:0] result;
wire [12:0] wshiftregister13;
wire [6:0] wshiftregister7;
wire zero, overflow;
wire shiftright, Write;
wire wstate,wdone;

initial begin
multiplicand[6:0]<=7'b000000;
product[13:0]<=14'b00000000000000;
stateregister[7:0]=8'b00000000;
shiftregister13[12:0]=13'b0000000000000;
shiftregister7[6:0]=7'b0000000;
end

always @(posedge iClk) begin
multiplicand[0]<=~iReset&wmultiplicand[0];
multiplicand[1]<=~iReset&wmultiplicand[1];
multiplicand[2]<=~iReset&wmultiplicand[2];
multiplicand[3]<=~iReset&wmultiplicand[3];
multiplicand[4]<=~iReset&wmultiplicand[4];
multiplicand[5]<=~iReset&wmultiplicand[5];
multiplicand[6]<=~iReset&wmultiplicand[6];
product[0]<=~iReset&w1product[0];
product[1]<=~iReset&w1product[1];
product[2]<=~iReset&w1product[2];
product[3]<=~iReset&w1product[3];
product[4]<=~iReset&w1product[4];
product[5]<=~iReset&w1product[5];
product[6]<=~iReset&w1product[6];
product[7]<=~iReset&w2product[0];
product[8]<=~iReset&w2product[1];
product[9]<=~iReset&w2product[2];
product[10]<=~iReset&w2product[3];
product[11]<=~iReset&w2product[4];
product[12]<=~iReset&w2product[5];
product[13]<=~iReset&w2product[6];
stateregister[0]<=~iReset&wstateregister[0];
stateregister[1]<=~iReset&wstateregister[1];
stateregister[2]<=~iReset&wstateregister[2];
stateregister[3]<=~iReset&wstateregister[3];
stateregister[4]<=~iReset&wstateregister[4];
stateregister[5]<=~iReset&wstateregister[5];
stateregister[6]<=~iReset&wstateregister[6];
stateregister[7]<=iReset|wstateregister[7];
shiftregister13[0]<=iReset&wshiftregister13[0];
shiftregister13[1]<=iReset&wshiftregister13[1];
shiftregister13[2]<=iReset&wshiftregister13[2];
shiftregister13[3]<=iReset&wshiftregister13[3];
shiftregister13[4]<=iReset&wshiftregister13[4];
shiftregister13[5]<=iReset&wshiftregister13[5];
shiftregister13[6]<=iReset&wshiftregister13[6];
shiftregister13[7]<=iReset&wshiftregister13[7];
shiftregister13[8]<=iReset&wshiftregister13[8];
shiftregister13[9]<=iReset&wshiftregister13[9];
shiftregister13[10]<=iReset&wshiftregister13[10];
shiftregister13[11]<=iReset&wshiftregister13[11];
shiftregister13[12]<=iReset&wshiftregister13[12];
shiftregister7[0]<=iReset&wshiftregister7[0];
shiftregister7[1]<=iReset&wshiftregister7[1];
shiftregister7[2]<=iReset&wshiftregister7[2];
shiftregister7[3]<=iReset&wshiftregister7[3];
shiftregister7[4]<=iReset&wshiftregister7[4];
shiftregister7[5]<=iReset&wshiftregister7[5];
shiftregister7[6]<=iReset&wshiftregister7[6];
end

ControlSignal_Multiplier cm00(iClk,product[0],shiftright,Write);

assign wmultiplicand[6:0]=iMultiplicand[6:0];

ALU_7bit_unsigned seven01(multiplicand, product[13:7], result, zero, overflow, 0,1,0);

Mux21to7_2bit mux300(iMultiplier,backproduct[6],backproduct[5],backproduct[4],backproduct[3],backproduct[2],backproduct[1],backproduct[0],product[6],product[5],product[4],product[3],product[2],product[1],product[0],w1product,iReady,shiftright);
Mux21to7_2bit mux301(result,0,backproduct[12],backproduct[11],backproduct[10],backproduct[9],backproduct[8],backproduct[7],product[13],product[12],product[11],product[10],product[9],product[8],product[7],w2product,Write,shiftright);
Mux26to13_1bit mux200(frontproduct,shiftregister13,wshiftregister13,~shiftright);
assign frontproduct[12:0]=product[13:1];
assign backproduct[12:0]=shiftregister13[12:0];

Mux16to8_1bit mux310(wstateregister,0,backstateregister[6],backstateregister[5],backstateregister[4],backstateregister[3],backstateregister[2],backstateregister[1],backstateregister[0],wstateregister,shiftright);
Mux14to7_1bit mux210(frontstateregister,shiftregister7,wshiftregister7,~shiftright);
assign frontstateregister[6:0]=stateregister[7:1];
assign backstateregister[6:0]=shiftregister7[6:0];

xor exclusive01(oProduct[15],iMultiplier[7],iMultiplicand[7]);
assign oProduct[14]=1'b0;
or pmor02(oProduct[0],product[0],stateregister[0]);
or pmor03(oProduct[1],product[1],stateregister[0]);
or pmor04(oProduct[2],product[2],stateregister[0]);
or pmor05(oProduct[3],product[3],stateregister[0]);
or pmor06(oProduct[4],product[4],stateregister[0]);
or pmor07(oProduct[5],product[5],stateregister[0]);
or pmor08(oProduct[6],product[6],stateregister[0]);
or pmor09(oProduct[7],product[7],stateregister[0]);
or pmor010(oProduct[8],product[8],stateregister[0]);
or pmor011(oProduct[9],product[9],stateregister[0]);
or pmor012(oProduct[10],product[10],stateregister[0]);
or pmor013(oProduct[11],product[11],stateregister[0]);
or pmor014(oProduct[12],product[12],stateregister[0]);
or pmor015(oProduct[13],product[13],stateregister[0]);

assign oDone=stateregister[0];

endmodule